Port 3C2-W  -  VGA Miscellaneous Output Register

        The read address for this register is 3CC and its write address
        is 3C2.

          1xxx xxxx  Vertical Sync Polarity
                       When set to 0, this bit selects a positive
                       'vertical retrace' signal. This bit works
                       with bit 6 to determine the vertical size.
          x1xx xxxx  Horizontal Sync Polarity
                       When set to 0, this bit selects a positive
                       'horizontal retrace' signal. Bits 7 and 6 select
                       the vertical size (see below).
          xx11 xxxx  Reserved
          xxxx 11xx  Clock Select
                       These two bits select the clock source according
                       to the figure below. The external clock es driven
                       through the auzilary video extension. The input
                       clock should be kept between 14.3 and 28.4 MHz.
          xxxx xx1x  Enable RAM
                       When set to 0, this bit disables address decode
                       for the display buffer from the system.
          xxxx xxx1  I/O Address Select
                       This bit select the CRT controller addresses.
                       When set to 0, this bit sets the CRT controller
                       addresses to 3Bx and the address for the Input
                       status register 1 to 3BA for compatibility with
                       the monochrome adapter.
                       When set to 1, this bit sets the CRT controller
                       addresses to 3Dx and the address for the Input
                       status register 1 to 3DA for compatibility with
                       the color/graphics adapter.
                       The Write addresses to the feauture control
                       register are affected in the same manner.


            Bits
            7 6    Vertical size
            --------------------
            0 0    Reserved
            0 1    400 lines
            1 0    350 lines
            1 1    480 lines


            Bits
            3 2    Clock Select
            --------------------
            0 0    Selects 25.175 MHz clock for 640/320 Horizontal PELs
            0 1    Selects 28.322 MHz clock for 720/360 Horizontal PELs
            1 0    Selects External Clock
            1 1    Reserved